AMD is currently seeking a Verification Engineer for their Hyderabad location. The ideal candidate for this role should possess at least a Bachelor’s or Master’s degree in computer engineering or electrical engineering. Key skills and qualifications required include a strong background in the C++ language, preferably on Linux with some exposure to the Windows platform. Additionally, candidates should have a good understanding and hands-on experience in UVM concepts and the SystemVerilog language, as well as a working knowledge of SystemC and TLM with related experience. Proficiency in scripting languages such as Perl, Ruby, Makefile, and shell is preferred. Exposure to leadership or mentorship roles is considered an asset for this position.
Company Name: AMD
Job Role: Verification Engineer
Education Required: Bachelors or Masters degree in computer engineering/Electrical Engineering.
Job Location: Hyderabad
Job Responsibilities:
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
- Estimate the time required to write the new feature tests and any required changes to the test environment.
- Build the directed and random verification test.
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.
Preferred Skills and Qualifications:
- Bachelors or Masters degree in computer engineering/Electrical Engineering.
- Proficient in IP level ASIC verification and Boot flows.
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux with exposure to Windows platform
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Good working knowledge of SystemC and TLM with some related experience.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assets with prior exposure to video codec system or other multimedia solutions.
